An embodiment of the present invention relates to a semiconductor device including a vertical transistor and a method for manufacturing the same.
In general, a semiconductor is a material which belongs to an intermediate region of a conductor and a nonconductor according to classification of materials based on electrical conductivity. Although a semiconductor is similar to a nonconductor in a pure state, the electrical conductivity of the semiconductor changes by addition of impurities or by other manipulations. The semiconductor has been used to produce a semiconductor device such as a transistor by addition of impurities and connection of the conductor. A semiconductor apparatus refers to an apparatus having various functions performed by the semiconductor device. A representative example of the semiconductor apparatus is a semiconductor memory apparatus.
A semiconductor memory apparatus comprises a plurality of unit cells each including a capacitor and a transistor. A double capacitor is used to store data temporarily, and a transistor is used to transfer data between a bit line and a capacitor in response to a control signal (word line) using an electrical conductivity change. A transistor includes three regions such as a gate, a source and a drain. In a transistor, charges between the source and the drain move in response to a control signal. The movement of charges between the source and the drain is performed through a channel region which has the property of the semiconductor.
When a general transistor is formed in a semiconductor substrate, a gate is formed in the semiconductor substrate, and impurities are doped at both sides of the gate so as to form a source and a drain. In this case, a space between the source and the drain under the gate is a channel region of the transistor. A transistor having a vertical channel region occupies given area of the semiconductor substrate. In case of a complicated semiconductor memory apparatus, it is difficult to reduce a unit cell area because the number of transistors included in a unit cell increases.
If a unit cell area of a semiconductor apparatus is reduced, it is possible to increase the number of net die per wafer, thereby improving productivity. In order to reduce a unit cell area of a semiconductor memory apparatus, various methods have been suggested. As one of these methods, a 3D transistor is used which includes a vertical transistor having a vertical channel region instead of a conventional planar transistor having a horizontal channel region.